Among various display systems are those that use light emitting diodes (LEDs) as display elements. Pulse Width Modulation (PWM) is widely used to adjust the brightness of LEDs. In applications involving LED panels, PWM has become a dominant approach to brightness control, due to its ability to support a massive number of LEDs and the simplicity of the methodology.
To reduce the number of input/output (IO) pins, PWM signals are often multiplexed in the LED array as shown in FIG. 21. FIG. 21 shows a conventional LED array 2101 that contains m×n LEDs (one shown as 2103), where m is the number of columns and n is number of rows (in this case, m=3, n=4). At any given moment, only a subset of the LEDs is activated by the PWM signals and each one in the subset is controlled by one pin. For example, vertical line 4 is driven low and four PWM signals are sent to pins 0, 1, 2 and 3. Once the first column is illuminated, vertical line 4 is released to high and vertical line 5 is driven low in order to refresh the middle column. This process continues until all m columns are refreshed. If the refreshing rate (i.e., the frame rate) is sufficiently fast, the persistence of vision allows the whole LED array to appear to be illuminated at the same time.
LED brightness values typically arrive at a display system as digital values, which are converted into a pulse width for application to a selected LED. If the PWM resolution is p bits (representing the color depth), in general, the frame rate (f) of the LED panel is governed by the following relationship:f∝(k/N)*(½pw)Were w is the minimum pulse width of a p-bit PWM signal (namely, color depth is p bits), N is the total number of LEDs and k is the number of IO pins. For example, using the conventions of FIG. 21, N=m×n, and k=2mn).From the above, the following can be observed regarding conventional LED array operations. (1) Increasing the number of IOs (k) leads to a reduced number of LEDs controlled per pin and therefore improves the frame rate. (2) Increasing the total number of LEDs (N) simply implies more tasks are to be finished by a given number of IOs and leads to lower frame rate. (3) Increasing the color depth (p) results in more time spent on each LED and therefore leads to lower frame rate. (4) Increasing the minimum pulse width of PWM signal (w) means a slower PWM signal, which produces a brighter image and lower frame rate.
Another observation is that the frame rate is directly proportional to the number of IOs (k) required to refresh all LEDs (N), which is often determined by the refreshing techniques. Table 1 below summarizes the total number of LEDs that can be controlled by k IO pins for different refreshing techniques.
TABLE 1Total numbers of LEDs controlled by k IO pinsNumbers of LEDs Techniquescontrolled by k IO pinsTraditional Multiplexingk2/4Charlieplexingk(k − 1)Conventional “Charlieplexing” is shown FIG. 22, and will be described in more detail at a later point herein.
For applications like three-dimensional (3D) displays, both the frame rate f and IO density (directly related to k) can be equally important. If one can refresh all LEDs with less number of pins (k) within a given period, it can lead to a simpler design and lower cost (less number of components). However, the traditional approach as shown in FIG. 21 cannot improve the fame rate without significantly increasing the number of IOs. To describe how efficiently an IO pin is utilized to control an LED panel, we define an IO frame rate efficiency (IOFRE) as follows:IOFRE=f/k∝(½pwN)Clearly, from the above equations, among the five parameters of frame rate (f), number of IO pins (k), color depth (p), PWM speed (w) and resolution (N), an unknown parameter is always determined by the other four known parameters. Thus, one cannot improve all of them using the approach as described above.
Conventional Charlieplexing is a popular multiplexing technique to control large numbers of LEDs, especially for applications such as LED displays. The basic principle is that there is only one pair of “1” and “0” at any time for n+1 pins and the rest of the pins are disconnected (i.e., in a high impedance, or “Hi-Z” state). Therefore, there are n(n+1) ways of using the (n+1) pins. FIG. 22 shows an LED array 2201 having a 3-pin Charlieplexing configuration which drives 6 LEDs (three shown as 2203-0/1/2). In this configuration, only one LED can be powered at a time. For example, to illuminate LED 2203-0, Y1, Y2, Y3 are required to be at 1 (i.e., high voltage), 0 (i.e., low voltage), and Hi-Z, respectively. One may notice that there appears to be two alternative LED paths (2203-1/2) when LED 2203-0 is active. However, since LED 2203-0 is activated first, it will clamp the voltage across LED 2203-1 and LED 2203-2 to its forward voltage. Half of the forward voltage drop is not able to drive either LED 2203-1 or 2203-2. Therefore, only one LED 2203-0 is visible.
FIG. 23 shows conventional Charlieplexing configuration 2301 for a set of red-green-blue (RGB) LEDs (2305-0 to -4). As shown, every row line (2307-1 to -4) shares the same cathodes of one RGB LED (LED group). Therefore, it is possible to control k*(3k+1) RGB LEDs with 3k+1 pins, where k=1, 2, 3 . . . . It is noted that we use 3k+1 (instead of n) to denote the number of pins for RGB Charlieplexing because it cannot support arbitrary number of pins (for example, 5=3*1+2). This means that each row contains k RGB LEDs (3k pins) and there are totally 3k+1 rows. FIG. 23 shows the configuration with k=1. In this configuration, each pin controls k RGB LEDs on average while the total number of pins is 3k+1.
One type of display can be a high frame rate (HFR) LED panel. Such panels are often used in 3D display applications. A drawback to conventional HFR LED panels can be the relatively high cost. Differences between HFR LED panels and traditional LED panels (with a lower frame rate) that can lead to higher costs include: (1) an extra-large number of components. To achieve a desired frame rate, a conventional HDR system can require hundreds or even thousands of control units which are implemented using one or more processors (CPUs) and/or field programmable gate arrays (FPGAs). Compared with a traditional low frame rate LED panel, where there is only one CPU, the number of components used in an HFR system is several orders of magnitude larger. (2) A complicated interconnect structure. With such a large number of components, the interconnection among them also significantly increases. One way to address the complicated interconnect structure is to use advanced process technology like a printed circuit board (PCB) with more layers and blind-vias. However, this also significantly increases the cost. Further, such complicated structures are more difficult to debug for problems.